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Intel P4 Platform Roadmap Analysis
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Intel P4 Platform Roadmap Analysis


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Intel P4 Platform Roadmap Analysis

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Sections
The Big Picture
The P4 Willamette Platform
The New P4 Northwood Processor
The New P4 Tualatin Processor
The New ICH3 Chip
Next generation Chipsets
Summary Analysis

Intel P4 Platform Roadmap Analysis

The New ICH3 Chip

In mid 2001, Intel will release its ICH3 chip (south bridge). The primary new feature of the ICH3 chip is the addition of USB2.0 (six ports!). Other than that, its primary features seem to be the same as the ICH2 - such as ATA100 support, integrated LAN interface, AC97 audio and modem capabilities, etc.

The ICH3 is the only point of differentiation between Tehama and TehamaE chip sets. The north bridge is constant. Intel will use the availability of the ICH3 as an additional catalyst to justify a board redesign to migrate from the P4's 423-pin package to the 478-pin package.

The ICH3 will show up first on P3 (Coppermine and Tualatin) platforms using the Almador chip set in mid Q2'01. It will be packaged in a 421 pin BGA.

Chip Sets: Brookdale

In July, Intel revealed that it has plans for an SDRAM chip set for its Pentium4 processor family. This chip set is named Brookdale, and is paired with the ICH3 chip. Brookdale will sample to OEMs and board manufacturers in early Q2'01 and will go to production in late Q3'01.

Current Intel documentation on Brookdale describes support for SDRAM only, mentioning exclusively PC133. However, direct feedback from OEMs indicate that when pressed, key Intel personnel will admit that it is a dual mode design supporting both DDR and SDR at the component level. OEMs will have to commit to either to DDR or SDR at board design time - both DRAM types cannot be supported in a single board implementation. In light of the availability of DDR support, it is extremely unlikely that any manufacturer (other than perhaps Intel) will do an SDR design.

Given today's competitive market, and Intel's probable need in Q3'01 to aggressively recover market share, common sense would suggest that a 64-bit PC133 platform design for the then 'fastest x86 processor on earth' is a formula for disaster. DDR will be in the mainstream well before Brookdale is ready in Q3'01. Intel does not have to evangelize this aspect of the chip set design in order to enable this transition. This gives Intel the emotional cushion it needs to ease back into the path of the rest of the industry - even if a bit late.

Still, OEMs speculate that at IDF in August, Intel marketing may hold to the message that Brookdale will support only single data rate PC133. The story from Intel engineering seems to be that Brookdale is a dual mode design, but that marketing will decide when and how to reveal that to the market. If marketing holds to the PC133 story at IDF, Intel may wait to reveal its DDR capability until some time after AMD customers successfully ramp DDR platforms to high volume production. If this sequence of events comes to pass, Intel might be forced to artificially spin off a unique DDR version of the chip with a different name in order to avoid further embarrassment.

The bottom line is that Brookdale needs to be the "Pentium4's BX chip set." The BX was designed to deliver flat out performance, with all of the features required in the market at the time. It was not manipulated by a marketing department, insisting that it should be made 'slower than Camino' or de-featured for some strange reason. Intel is in desperate need of an unqualified hit, a decisive win, in the platform department. If the marketing department can understand this and let the engineers do their job, Brookdale will impress the world with an unmatched ability to extract every ounce of performance available from low cost PC266 SDRAM. The world might once again stand in awe.

Chip Sets: Almador

Almador has been in the industry rumor mills for several months. It is understood to be a DDR/SDR follow on to the 815 chip set. It will be used with Coppermine and Tualatin processors. DDR support, if implemented at the board level, will boost the performance of the integrated 3D graphics controller and offer DRAM bandwidth matched to a possible 200MHz front side bus.

Though DDR support in Almador would help it to complete with Athlon, SDR would still have a place in low-end systems. We are at a loss, however, to imagine what real advantage an SDR Almador might have over the existing 815 for the low-end markets.

As a side observation, the currently integrated 740 graphics accelerator is showing its age, and Intel is in need of a new 3D graphics core for integration into future chip sets. It seems unlikely that Intel would re-architect its current 740-style 3D core. Rather, it is seems more logical that Intel would search outside for a higher performance licensable 3D core from yet another third party.

Though there are a number of possibilities, a tile based rendering approach (such as from Gigapixel - recently acquired by 3dfx) might be an interesting option for several reasons. Tile based 3D accelerator designs can consume lots of silicon, but deliver admirable performance with a very low external bandwidth budget. We currently have no particular insight on Intel's future graphics integration strategy, but merely offer this commentary as food for thought.

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